This invention relates generally to an input/output structure for an integrated circuit and, in particular, to an output driver using thin and thick gate oxides.
As integrated circuit (IC) designs become more complex, IC developers are moving toward smaller geometries to provide these designs without sacrificing valuable board space. However, smaller geometries require lower power supply voltages due to transistor breakdown. Specifically, for a given power supply voltage, the electric field strength, i.e. the change in voltage per unit length, that a transistor is exposed to increases as the size of the transistor is reduced.
The maximum electric field tolerance can be a limiting factor on the minimum transistor size. For example, a typical maximum gate oxide field strength for silicon dioxide gates is about 3 megavolts per centimeter. High electric fields inside a transistor can reduce the mean time to failure, and can destroy transistors when an electric field exceeds the breakdown value for a given material in a transistor, such as the gate oxide in CMOS devices. Therefore, in 0.35 xcexcm CMOS technology, a typical power supply of 3.3 Volts (a maximum power supply of 3.3 Volts+10%) is provided, whereas in 0.25 xcexcm CMOS technology, a typical power supply of 2.5 Volts (a maximum power supply of 2.5 Volts+10%) is provided.
An IC typically has a plurality of input/output (I/O) circuits that act as an interface between the internal circuits of the IC and the environment external to the IC. FIG. 1 illustrates a typical I/O circuit 100 that includes an input driver 101 and an output driver 103. Output driver 103 drives an electrical signal generated by one or more internal circuits that provide a function f to a pad 104 that is connected to the external environment. Input driver receives a signal from the external environment through pad 104 and drives that signal to one or more internal circuits 102.
When two ICs having different power supply levels are coupled together, the I/O circuit is generally required to prevent damage to transistors in the device having the lower power supply level. For example, in one illustrative technology, the XC9500XL(trademark) complex programmable logic device (CPLD), available from Xilinx, Inc., has 5 Volt tolerant I/O pins that accept 5 Volt, 3.3 Volt, and 2.5 Volt signals.
To further complicate IC design, some IC structures are exposed to different voltages on chip. For example, the XC9500XL CPLD includes an on-chip charge pump that generates high voltages of, in one embodiment, +8 Volts or xe2x88x928 Volts. Transistors that transfer such high voltages require corresponding thick gate oxides to prevent transistor breakdown. However, the flash memory cells of the XC9500XL CPLD are programmed/erased by these high voltages. Therefore, these memory cells require an intermediate gate oxide thickness. Finally, standard logic in the XC9500XL CPLD is not exposed to the high voltages of the charge pump and thus transistors that comprise the standard logic require only a thin gate oxide.
The thicknesses vary depending on the technology. For example, in the XC9500XL CPLD implemented in 0.35 xcexcm technology, devices have gate oxide thicknesses of 150 Angstroms, 100 Angstroms and 70 Angstroms. The 150 Angstrom thickness is used for transistors transferring the large voltages generated by the charge pump. The 100 Angstrom thickness is used for the tunneling oxide of the memory cells, i.e., between the floating gate and the substrate. (Note that the thickness of the oxide between the control gate of such a memory cell and the floating gate is typically 150 Angstroms). Finally, the 70 Angstrom thickness is used for the transistors comprising the standard logic, including the I/O circuitry.
Because of its interface to external circuits, the I/O circuitry is of particular concern to IC designers. Specifically, output drivers should provide a fast I/O delay when driving a predetermined capacitive load while protecting all transistors in the output driver from high voltages on the I/O pad. FIG. 2 illustrates a prior art, output driver 200 in a XC9500XL CPLD. Output driver 200 includes a pull-up transistor 205 coupled between an I/O voltage supply Vddio and an I/O pad 211. Output driver 200 further includes a pull-down transistor 209 and an isolation transistor 210 coupled in series between a ground voltage and pad 211. Isolation transistor 210 has its gate coupled to an internal supply voltage Vddint and therefore is conducting. In one embodiment, voltage Vddint is 3.3V.
In an enable (output) mode, either pull-up transistor 205 or pull-down transistor 209 is on, thereby providing the appropriate output data DOUT signal to pad 211. In contrast, in a tristate mode, both transistors 205 and 209 are off, thereby allowing pad 211 to provide an input signal to an input driver (not shown) and thereafter to the internal circuits (also not shown) of the PLD.
Input drivers are well known in the art and therefore are not described in detail herein. The internal circuits of the XC9500XL device are described in detail on pages 5-5 to 5-15 of xe2x80x9cThe 1999 Programmable Logic Data Bookxe2x80x9d, published by Xilinx, Inc. and incorporated by reference herein.
Output driver 200 receives an output enable signal OE that determines whether output driver 200 is tristated or active. In the tristate mode, when the output enable signal OE is low, then an inverter 201 provides a high signal to an input terminal of a NOR gate 202, thereby ensuring that NOR gate 202 outputs a low signal. An inverter 203 inverts this low signal. A protection transistor 204 has the I/O voltage Vddio applied to its gate. Voltage Vddio turns on protection transistor 204, thereby transferring the high signal output from inverter 203 (less one threshold voltage of its associated NMOS transistor) to the gate of pull-up transistor 205 and turning off that transistor. Note that the power supply provided to the logic of output driver 200, unless otherwise noted, is voltage Vddint.
Also in the tristate mode, the low OE signal is provided to an input terminal of NAND gate 207, thereby ensuring that NAND gate 207 outputs a high signal. An inverter 208 inverts that high signal and therefore provides a low signal to the gate of pull-down transistor 209. In this manner, transistor 209 is also turned off.
In the active mode, a high OE signal results in a low signal provided to NOR gate 202 and a high signal provided to NAND gate 207. Therefore, the output signals of those gates depend on the state of the data output DOUT signal. If DOUT is high, then both NOR gate 202 and NAND gate 207 output a low signal. In this manner, transistor 205 is turned off, but transistor 209 is turned on, thereby providing a low signal on pad 211. Thus, driver 200 provides an inverted DOUT signal on pad 211 during the active mode.
On the other hand, if DOUT is low, then both NOR gate 202 and NAND gate 207 outputs a high signal. In this manner, transistor 209 is turned off, but transistor 205 is turned on, thereby providing a high signal on pad 211.
Pull-down transistor 209 must be protected when pad 211 is used as an input pin and carries a voltage up to 5.5V. Isolation transistor 210 has its gate connected to Vddint (3.3 Volts) and thus the voltage at the drain of pull-down transistor 209 is no more than Vddint minus an NMOS threshold drop (i.e., 3.6xe2x88x920.7=2.9). Therefore, transistor 209, which can withstand a junction (gate to source or gate to drain) voltage of 3.6 Volts, will not experience damaging voltage levels.
Pull-up transistor 205 must be prevented from conducting current to Vddio (3.3 Volts or 2.5 Volts) when pad 211 is used as an input pin and carries a voltage up to 5.5V. Thus, output driver 200 includes a well driver 206 that maintains a sufficiently high voltage to the well and the gate of pull-up transistor 205 to prevent leakage current through this transistor. One known well driver is described in U.S. Pat. 5,933,025, entitled xe2x80x9cLow Voltage Interface Circuit With A High Voltage Tolerancexe2x80x9d, which is incorporated by reference herein. Other, conventional well drivers are well known to those skilled in the art and therefore are not described in detail herein.
As noted previously, the transistors in the I/O circuitry, including driver 200, are comprised of transistors having an oxide thickness of 70 Angstroms. The channel widths and lengths for the PMOS and NMOS transistors of output driver 200 are as follows: Wp=228 xcexcm, Lp=0.35 xcexcm, Wn=220 xcexcm, and Ln=0.35 xcexcm (wherein xe2x80x9cpxe2x80x9d designates a PMOS transistor, and xe2x80x9cnxe2x80x9d designates an NMOS transistor).
Output driver 200, implemented with transistors having a gate oxide thickness of 70 Angstroms, has two advantages. First, output driver 200 can protect its transistors from standard high voltages on pad 211 including both 3.3 Volts and 5 Volts. Second, the I/O delay (i.e., the time from the input terminal of inverter 201 to pad 211) is acceptable at 2.30 nanoseconds for driving a capacitive load 212. In a typical embodiment, capacitive load 212 is approximately 35 picofarad.
If the XC9500XL CPLD is implemented in 0.25 xcexcm technology, transistors in this device have gate oxide thicknesses of 150 Angstroms, 100 Angstroms and 50 Angstroms. As described previously, the gate oxide thickness of 150 Angstroms is used for transistors transferring the large voltages generated by the on-chip charge pump. The gate oxide thickness of 100 Angstroms is used for the memory cells on the chip. Finally, the gate oxide thickness of 50 Angstroms is used for the transistors comprising the remainder of the logic, including the I/O circuitry. The channel widths and lengths for the PMOS and NMOS transistors of output driver 200 (as well as any standard transistors) are as follows: Wp=228 xcexcm, Lp=0.25 xcexcm, Wn=220 xcexcm, and Ln=0.25 xcexcm Note that in 0.25 micron technology, internal voltage Vddint is 2.5 Volts.
Output driver 200, implemented with transistors having a gate oxide thickness of 50 Angstroms, has both advantages and disadvantages. Specifically, because of the thinner oxide (and thus lower threshold voltage and more rapidly achieved saturation current), these transistors can turn on/off faster than thicker oxide transistors. Thus, in this implementation, output driver 200 has a faster I/O delay of only 1.60 nanoseconds driving the same capacitive load 212.
However, as explained below, output driver 200 can no longer provide an I/O voltage Vddio of 3.3 Volts to pad 211, thereby limiting the type of external devices coupled to device 100. Specifically, because the oxide thickness is only 50 Angstroms, a conducting transistor can have a maximum voltage of 2.75V (2.5V+10%) across any junction (i.e., gate to source or gate to drain). If the gate of transistor 205 were grounded, thereby turning on pull-up transistor 205, then a maximum voltage Vddio of 3.6 Volts on its source would exceed the maximum permissible junction voltage. Therefore, output voltage Vddio in this embodiment of output driver 200 is limited to either 2.5 Volts or 1.8 Volts.
Moreover, output driver 200 has an I/O tolerance limited to 3.3 Volts. Specifically, as described above, a conducting transistor having a gate oxide thickness of 50 Angstroms can have a maximum voltage of 2.75 Volts (2.5 Volts+10%) across any junction (i.e., gate to source or gate to drain). If the gate of isolation transistor 210 receives a Vddio of 2.25 Volts (2.5 Voltsxe2x88x9210%)), thereby turning on isolation transistor 210, then a voltage on pad 211 of 5.5 Volts would exceed the maximum permissible junction voltage (5.5xe2x88x922.25=3.25). Therefore, the I/O tolerance in this embodiment of output driver 200 is limited to a voltage of 3.3 Volts (3.6xe2x88x922.25=1.45) or less.
Due to current fabrication techniques, fabrication houses have established an industry standard limited to three gate oxide thicknesses. Thus, although providing pull-up transistor 205 with a gate oxide thickness of 70 Angstroms would solve the junction voltage problem by increasing the permissible junction voltage to 3.6 Volts, an IC implemented in 0.25 micron technology is currently limited to transistors having gate oxide thicknesses of 150, 100, or 50 Angstroms.
Therefore, a need arises for an output driver providing maximum choices of output voltages while operating within industry fabrication standards.
An output driver of the present invention includes a first pull-up transistor coupled to a pad of an integrated circuit. The first pull-up transistor has a thick gate oxide, thereby ensuring that the output driver can provide a full range of industry standard output (Vddio) voltages. In one embodiment, these voltages include 3.3 Volts, 2.5 Volts, and 1.8 Volts.
In one embodiment, the output driver further includes a second pull-up transistor coupled to the pad. The second pull-up transistor-has a thin gate oxide, thereby ensuring a fast low-to-high voltage transition on the pad. In this embodiment, the gate oxide thicknesses of the first and second pull-up transistors are 150 Angstroms and 50 Angstroms, respectively.
In accordance with this embodiment of the present invention, the first and second pull-up transistors are sized to minimize use of silicon resources, while at the same time provide satisfactory drive current and switching time (i.e., low-to-high transitions). For example, the output driver of the invention typically requires approximately 20% less area than standard output drivers.
In one embodiment, the sources of the first and second pull-up transistors are coupled to different voltages. For example, the source of the first pull-up transistor may be coupled to any industry standard output voltage, as mentioned above, whereas the source of the second pull-up transistor is only coupled to the internal voltage supply of the IC (such as 2.5 Volts). The output driver also includes a pull-down transistor having a source coupled to a second predetermined voltage (such as ground) and a drain coupled to the pad.
The pull-down transistor and the two pull-up transistors are selectively disabled by a logic circuit. Specifically, the gates of these transistors are coupled to the logic circuit that provides an output enable signal. In one state, a tristate mode, the pull-down transistor and the two pull-up transistors are turned off, thereby allowing an input signal to be placed on the pad. In the other state, the enable mode, the data out signal determines whether the pull-down transistor is turned on (and the pull-up transistors are turned off), or the pull-up transistors are turned on (and the pull-down transistor is turned off).
In one embodiment, the output driver includes a protection transistor having a gate coupled to the output voltage supply, a drain coupled to a gate of the first pull-up transistor, and a source coupled to receive an output signal of the logic circuit (the output enable signal as well as the data out signals). To protect the pull-down transistor and the second pull-up transistor from high voltages on the pad, an isolation transistor may also be provided. This isolation transistor has a gate coupled to the internal voltage supply, a drain coupled to the pad, and a source coupled to the pull-down and the second pull-up transistors.
In one embodiment, the output driver includes a logic shifter for receiving the output signal of the logic circuit and providing an output signal to the gate of the first pull-up transistor. If the level shifter inverter receives a high internal signal, such as 2.5 Volts, then the inverter outputs a low output signal (typically 0 Volts). However, if the level shifter inverter receives a low internal signal (0 Volts), then the inverter outputs a high output signal at a different level than the high internal signal (such as 3.3 Volts). In this manner, the output driver ensures that the first pull-up transistor is turned off during the tristate mode as well as during the active mode when the data out signal is high (wherein the output driver provides an inverted data out signal). In one embodiment, the output driver is used in combination with an input driver to form an input/output (I/O) structure on the IC. The input driver provides an input signal on the I/O pad to the internal circuitry of the IC.